1. Field of the Invention
The present invention generally relates to methods of integrated circuit checking and verification and more particularly to methods of integrated circuit wiring checking and verification.
2. Background Description
Advances in integrated circuit (IC) chip wiring technology have improved circuit performance and density, simultaneously with reducing IC chip cost. Both circuit density and the number of wireable circuits on an IC chip have been increased through wire feature scaling to reduce metal line pitch and contact pitch, in combination with increasing the number of available wiring layers.
The increase in the number of circuits on a single chip has led to a corresponding increase in the number of chip connection pads for chip inputs/outputs (I/Os) and for supplying power and ground to the chip. Consequently, to take full advantage of this increased IC chip gate count and complexity and to provide more locations for chip pad connections, standard chip images such as chip image 100 in FIG. 1 cannot be used.
Standard chip images 100 have well defined circumferentially located I/O cells 102 and predefined power busses. These prior art standard chip images 100 included circumferentially located electrostatic discharge (ESD) protection devices (not shown) connected to the circuit in the I/O cell 102 and an external connection pad 104. Each ESD device is meant to absorb the charge in the ESD event and, thereby, protect the I/O circuit from static electricity damage.
Typically, prior art ESD devices were designed and located based on well understood requirements of the particular circuit, cell and the physical characteristics of the ESD protect device. Thus, for a single power supply chip, the ESD device may have been, merely, a pair of reverse biased diodes, each connected between a supply or its return line (ground) and the I/O pad 104.
However, on a multiple supply chip, besides providing a ground discharge path, paths must be provided between each pad 104 and each power supply. Also, protect devices are typically required between supply pads 104. Thus, for a 2-supply chip, even an I/O cell 102 with a circuit connected to only to a single supply would require an ESD path between the connecting pad and the unused (by that I/O circuit) supply. This requirement makes wiring an already complex chip even more difficult.
The added level of complexity for prior art standard image 100 chips was minimal. The I/O circuit to pad 104 connections are pre-defined and fixed on a standard image 100, so the electrical characteristics of the connections are guaranteed.
These electrical characteristics are determined by type of wiring metal (aluminum or copper, etc.), as well as wire and via (inter metal-metal layer connections) dimensions, i.e., widths, lengths, thicknesses and contact sizes. Thus, by design, each individual I/O cell may have a fixed, well defined internal resistance associated with it, thereby assuring that the ratio of fixed wire resistance to internal cell resistance.
Further, multiple supply standard images 100 are designed with larger circumferential power busses that increases supply capacitance, which further reduces supply ESD sensitivity. So, because the power bussing is well defined, the requisite inter-supply ESD protect devices may be hid in unoccupied spaces among the I/O cells 102 of the circumferential I/O footprint. Additionally, regardless of which of the power supply lines any particular I/O circuit actually uses, all supply lines are routed to ESD protect devices for the I/O cell 102. Consequently, the I/O cells 102 can be checked, readily, to verify that ESD protect devices are includes, guaranteeing their inclusion where necessary and, in a predetermined ratio with the signal I/O cells.
However, with the increased I/O count requirement on state of the art IC chips, I/O cell placement is not restricted to the chip's periphery, the normal location for ESD devices. Instead, with an area array footprint, wires connecting I/O circuits to the I/O pads are routed either automatically by a design system or, interactively by a designer. Power busses are not as well defined and do not provided the extra protection from the added capacitance found on prior art standard images 100.
However, the net wires must still meet pre-determined electrical constraints determined by each included wiring layer's thickness and metallurgy in combination with the particular net's wire widths, which may vary from net to net. So, to guarantee ESD protection level, the interconnection routing must meets some minimum wire width constraint on each wiring layer and some minimum via size and number.
Thus, there is a need for integrated circuit chips with pad array interconnections having robust ESD protection.